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Reset and Reset Configuration
Table 5-2. E 2 PROM Hard Reset Configuration Word (continued)
Field
CS10PC
ALD_EN
Data
Bus
Bits
24:25
26
Prog
Value
[Bin]
’01’
’0’
Implication
CS10~/BCTL1/DBG_DIS~ functions as BCTL1
PCI Auto Load Enable. When high, PCI Bridge
Offset In
Flash
[Hex]
18
Value
[Hex]
5A
Configuration is done automatically from the
FLASH/E 2 PROM (CPM is configuration source
- PPC core should be disabled) right after the
Hard Configuration Word. When low, the PPC
Core should configure the PCI Bridge.
PCI_MODCK
27
’1’
Determines PCI clock settings as set by
PCI_MODCKH:
‘0’ - PCI clock set by PCI_MODCKH
‘1’ - PCI clock is divided according to
PCI_MODCKH
MODCK_HI 1
28:31
‘1010’
Determines the Core’s frequency out of
power-up reset.
1
Applies only ONCE after power-up reset.
The PCI configuration registers which are set at hard reset sequence are shown in Figure 5-1
Reserved
Address
Offset (Hex)
Device ID (0x18C0)
PCI Status
Vendor ID (0x1057)
PCI Command
00
04
Class Code
BIST Control
Subclass Code
Header Type
Standard Programming
Latency Timer
Revision ID
Cache Line Size
08
0C
PIMMR Base Address Register
10
14
18
Subsystem ID
Capability Pointer
////////
Subsystem Vendor ID
2C
34
38
MAX LAT
MIN GNT
Interrupt Pin
Interrupt Line
3C
////////
40
PCI Arbiter Control
PCI Function
44
Figure 5-1. PCI Host Configuration Registers
5.1.4
Soft Reset
Soft reset may be generated on the board from the following sources:
?
?
COP/JTAG port
Manual soft reset
Chapter 5. Module Design
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